Static random access memory (SRAM) integrated circuits (ICs) are widely used, both as stand alone memories and as embedded memories in, for example, microprocessors. The size of such SRAM ICs has increased markedly so that memories in excess of one million bits are now common. As IC size has increased, so has the processing complexity. The increased IC size requires a reduction in the size of individual components and in the minimum feature size, the minimum width of lines and spaces within an individual component. Processing complexity increases as the feature size decreases at least in part because it becomes difficult to precisely define lines and to insure adequate spacing between features. There are practical limits as to how much the minimum feature size can be reduced. At the limit it becomes difficult to reliably fabricate ICs with acceptable performance characteristics and at a reasonable yield. Thus as memory size continues to increase, it becomes incumbent on circuit designers and fabricators to find ways to decrease the size of a basic memory cell that goes beyond merely reducing feature size.
Accordingly, it is desirable to provide SRAM integrated circuits having a stacked memory cell. In addition, it is desirable to provide methods for fabricating SRAM integrated circuits having reduced size, stacked memory cells. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.